For decades, semiconductor progress has depended on finding new ways to place more transistors within the same amount of silicon. When conventional planar transistors reached their limits, the industry moved to three-dimensional FinFETs. As FinFET scaling became increasingly difficult, gate-all-around nanosheet transistors emerged as the next major architecture. But even gate-all-around technology has physical limitations. Eventually, shrinking transistors horizontally becomes extraordinarily difficult. The semiconductor industry is therefore beginning to explore another direction: up. Complementary field-effect transistors, or CFETs, vertically stack the two fundamental transistor types used in CMOS logic. If successfully commercialized, CFETs could represent one of the most significant changes to transistor architecture in decades.
From Planar Transistors to Vertical Scaling
The history of semiconductor scaling is increasingly a history of three-dimensional engineering.
Traditional planar transistors placed the source, drain, channel, and gate primarily along the surface of a silicon wafer. As transistor dimensions decreased, controlling electrical current through increasingly short channels became more difficult.
FinFETs addressed this problem by raising the transistor channel into a vertical fin and wrapping the gate around three sides. This provided greater electrical control while allowing transistor scaling to continue.
Gate-all-around nanosheet transistors take the concept further. Instead of a single vertical fin, several extremely thin horizontal semiconductor sheets are stacked vertically, with the gate surrounding each channel.
The architecture improves electrostatic control and allows engineers to adjust nanosheet dimensions to optimize performance and power consumption.
But there is another dimension that remains available for scaling.
Instead of placing neighboring transistors beside each other, engineers can place them on top of each other.
That is the fundamental idea behind CFET.
What Is a CFET?
Modern CMOS logic uses two complementary transistor types: nMOS and pMOS.
Traditionally, these devices are positioned next to one another on the silicon surface. That horizontal separation consumes valuable chip area.
A CFET changes the geometry.
Rather than placing the n-type and p-type devices side by side, the two transistor structures are vertically stacked within approximately the same footprint. One device occupies the lower tier while the complementary device sits above it.
The result is effectively a three-dimensional CMOS transistor structure.
By removing the horizontal spacing normally required between nMOS and pMOS devices, engineers can reduce the dimensions of the standard cells used to construct processors and other logic circuits. Imec’s current roadmap identifies CFETs as a candidate for future generations beyond today’s gate-all-around nanosheet architectures, with its research targeting introduction around the A7 technology generation.
Why Transistor Density Is Becoming a Different Problem
Historically, transistor scaling was closely associated with shrinking individual device dimensions.
That relationship is becoming less straightforward.
Even when engineers successfully shrink individual transistor features, the surrounding electrical contacts, power connections, interconnects, and spacing requirements consume substantial chip area. Improving transistor density therefore increasingly requires optimizing the entire standard cell rather than simply reducing gate length.
CFET directly addresses this problem.
Vertical stacking eliminates n-to-p spacing from the standard cell’s horizontal footprint. Imec’s recent research suggests CFET architectures could enable standard cells with approximately 4.5 tracks or fewer, allowing logic density to continue increasing as conventional lateral scaling becomes more difficult.
This represents an important shift in semiconductor engineering.
Future scaling may depend less on making every structure smaller and more on arranging those structures differently.
Two Different Paths to CFET Manufacturing
Building vertically stacked transistors is considerably more difficult than drawing them in a diagram.
Researchers are currently exploring two primary approaches: monolithic and sequential CFET integration.
In a monolithic CFET, the semiconductor layers required for both transistor types are incorporated into a vertically integrated structure and processed through a highly coordinated manufacturing sequence. This can create a compact architecture but requires extremely precise fabrication of complex, high-aspect-ratio structures.
Sequential CFET takes a different approach.
One transistor tier can be fabricated first, followed by the addition of another semiconductor layer and fabrication of the second transistor tier. Layer-transfer and wafer-bonding techniques can provide greater flexibility, including the possibility of using different semiconductor materials for the upper and lower devices.
Each approach presents tradeoffs involving manufacturing complexity, alignment, thermal budgets, performance, and cost.
Determining which approach is most suitable for high-volume manufacturing remains an important area of semiconductor research.
Connecting the Bottom Transistor Is Surprisingly Difficult
Stacking transistors creates another problem: engineers still have to connect them.
When both devices are positioned on the same surface, electrical contacts can be routed using established manufacturing techniques. Once one transistor sits underneath another, accessing the lower device becomes significantly more complicated.
Contacts must reach the source, drain, and gate structures without interfering with the transistor above them.
One potential solution is backside connectivity.
Instead of routing every connection through the front of the wafer, some electrical contacts can approach the lower transistor from the backside. Imec has demonstrated functional monolithic CFET structures using backside contacts, illustrating how backside processing could become an important companion technology to vertical transistor architectures.
This also connects CFET development to another major semiconductor trend: backside power delivery.
The future transistor may therefore be vertically stacked while receiving some of its electrical connections from beneath the wafer.
Manufacturing Complexity Becomes the Tradeoff
CFETs provide significant density advantages, but they introduce formidable manufacturing challenges.
Fabricating vertically stacked transistor structures requires extraordinarily precise deposition, etching, patterning, isolation, and alignment. Engineers must form electrical contacts within increasingly narrow spaces while ensuring that manufacturing the upper transistor does not damage the lower device.
Thermal budgets are particularly important.
Many semiconductor manufacturing processes require high temperatures. If the lower transistor has already been fabricated, subsequent processing must avoid altering its carefully engineered materials and electrical characteristics.
Vertical isolation is another challenge. The upper and lower devices must operate independently despite being separated by extremely small distances.
These issues explain why CFET remains primarily a research and development technology rather than a near-term replacement for today’s transistor architectures.
The concept is compelling. Manufacturing it economically across billions of transistors is the difficult part.
New Materials Could Push CFETs Even Further
Silicon may not be the final material used in CFET architectures.
Researchers are investigating atomically thin two-dimensional semiconductor materials that could eventually form transistor channels only a few atoms thick. Materials such as transition-metal dichalcogenides offer potentially attractive electrostatic characteristics while also enabling processing at temperatures compatible with certain forms of three-dimensional integration.
A 2026 Nature Communications perspective identified 2D materials as a promising pathway for future monolithic CFET architectures, while highlighting substantial challenges involving material synthesis, contacts, dielectrics, and integration.
This raises an intriguing possibility.
CFET may not simply be another generation of silicon transistor. It could eventually become the architecture that helps transition advanced logic toward entirely new semiconductor materials.
Moore’s Law Is Becoming Three-Dimensional
CFET illustrates how the meaning of semiconductor scaling is changing.
For much of the industry’s history, Moore’s Law was achieved primarily by shrinking structures across the surface of a wafer.
Increasingly, the industry is exploiting the vertical dimension.
Nanosheets stack transistor channels. Backside power moves electrical delivery beneath the devices. Chiplets and advanced packaging stack entire semiconductor dies. High-bandwidth memory stacks memory layers vertically.
CFET applies the same principle at one of the smallest and most fundamental levels of the semiconductor hierarchy: the individual CMOS transistor pair.
Instead of asking how much smaller a transistor can become, engineers are beginning to ask how much functionality can occupy the same footprint.
Looking Ahead
Gate-all-around nanosheet transistors are only beginning their commercial era, meaning CFETs are unlikely to replace them immediately. The manufacturing ecosystem must first master several generations of nanosheet technology while researchers continue solving the enormous fabrication challenges associated with vertically stacked complementary devices.
But the direction of semiconductor scaling is becoming increasingly clear.
The industry’s future will not depend exclusively on shrinking structures horizontally. Performance and density improvements will increasingly come from vertical integration at nearly every level of the computing system.
CFET represents perhaps the clearest expression of that transition.
The semiconductor industry spent decades making transistors smaller. The next era may be defined by something different: putting one transistor on top of another.