For decades, the semiconductor industry was guided by Moore’s Law—the observation that the number of transistors on an integrated circuit doubles approximately every two years, leading to increased performance and reduced cost per function. This empirical law was made possible through relentless transistor scaling: shrinking device geometries to fit more transistors into the same silicon area. However, as transistor dimensions have approached the nanometer scale, fundamental limits of physics have emerged, prompting a reassessment of the benefits and costs of “smaller.”
At the heart of the challenge is the behavior of electrons at nanoscale dimensions. Traditional metal-oxide-semiconductor field-effect transistors (MOSFETs) operate by creating a potential barrier to control current flow between the source and drain terminals. When the gate length—the distance between source and drain—shrinks below 10 nanometers, several quantum mechanical effects begin to dominate. One such effect is quantum tunneling, where electrons pass through the gate barrier even when it’s technically “off.” This leakage current increases static power consumption and undermines the device’s ability to switch reliably.
Another consequence of aggressive scaling is short-channel effects, where the electric field from the drain begins to interfere with the gate’s control over the channel. This results in degraded subthreshold performance, increased variability, and greater susceptibility to noise. These issues reduce the effective switching threshold and increase off-state leakage, contributing to performance instability and heat buildup. As a result, energy efficiency—once a natural byproduct of scaling—now declines without major architectural changes.
To address these limitations, the industry has introduced new transistor architectures and materials. FinFETs (fin field-effect transistors), first commercialized at the 22nm node, replaced planar designs with 3D fin structures that offer improved gate control by surrounding the channel on multiple sides. This was followed by gate-all-around (GAA) transistors, such as nanosheet or nanowire FETs, which fully encase the channel and allow for adjustable channel width based on performance or power requirements. Samsung and TSMC are deploying GAA designs at the 3nm node and below.
Material innovations have also played a crucial role. High-k dielectrics (e.g., hafnium oxide) replaced silicon dioxide in the gate insulator to reduce leakage and improve capacitance. Strained silicon and germanium channels were introduced to enhance carrier mobility. More recently, researchers are investigating two-dimensional materials such as molybdenum disulfide (MoS₂) and transition metal dichalcogenides (TMDs), which promise excellent electrostatic control and ultra-thin channel dimensions suitable for continued scaling.
Despite these breakthroughs, the economics of scaling have changed dramatically. The cost of developing a leading-edge process node can exceed $10 billion, and only a handful of companies—TSMC, Intel, and Samsung—have the capital and talent to operate at these bleeding-edge dimensions. Yield challenges, tool complexity (e.g., EUV lithography), and supply chain dependencies further complicate the path forward. As a result, many chipmakers are now embracing a “More-than-Moore” philosophy: prioritizing system-level innovation, heterogeneous integration, and chiplet architectures over further transistor shrinkage.
Moreover, some applications simply do not benefit from the densest possible transistors. In edge computing, analog signal processing, and power electronics, factors like robustness, thermal tolerance, and integration flexibility often outweigh maximum density. As such, the push for smaller is now complemented by a push for smarter—leveraging packaging innovations, energy-aware design, and application-specific optimization to achieve performance goals.
In short, while transistor scaling continues—now well into the angstrom era—it is no longer synonymous with progress. The physics of electrons, heat, and quantum mechanics set immutable boundaries. The future of microelectronics will be shaped not just by how small we can go, but by how wisely we balance complexity, efficiency, and architectural elegance at every scale.